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6980592 - consider, thatMessage rates may apply. Modems, methods, and computer program products for selecting an optimum data rate using error signals representing the difference between the output of an equalizer and the output of a slicer or detector. Neuer, unbenutzter und unbeschädigter Artikel in der ungeöffneten Originalverpackung soweit eine Verpackung vorhanden ist. When we will receive the parcel back next day we send money by paypal. Thank you, your vote was recorded and will show soon. English, Spanish, German, Swedish. Wie altes Wissen die Medizin verändert.
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The slicer in the error estimator creates the sliced signal from the maximum value detected. The threshold of the slicer is equal to the maximum value divided by two i.
The error estimator stores the total absolute error detected using each of the available IIR filters e. After each of the available IIR filters are tested, the error estimator and the control block outputs the selection of the IIR filter providing the least absolute error.
In operation, the filter selector waits samples for the IIR filter transient to be completed. The next data samples are used by the peak detector to find the maximum value of the input IIR filtered data, and the last data samples are used by the error estimator to calculate the total absolute error.
In particular, as shown in FIGS. As shown in FIG. In the implementation of FIGS. The remaining eight bits are used to store the small corrections to the coefficients — , and thus adaptively adjusts the FIR filter The FIR filter preferably includes an adaptive algorithm, e.
The FIR filter outputs 8-bit samples, and implements the following equations. In particular, the slicer implements the following equations: The coefficients — in FIG.
The step size in the adaptive FIR filter is a number always lower than one, e. The step size is reduced as the algorithm converges, and can be set equal to zero i.
Some alarms to be transmitted have this characteristic. A periodic pattern causes a major problem to equalization algorithms. This issue is solved, e.
When a periodic pattern is detected by the periodic pattern detector , the adaptive equalization is frozen and the output samples come directly from the periodic pattern detector While the invention has been described with reference to the exemplary embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention.
A SumoBrain Solutions Company. Search Expert Search Quick Search. United States Patent A filter selector block selects a desired set of coefficients corresponding to the optimum IIR filter.
A restored T1 or E1 signal is output from the FIR filter, and thus from the digital adaptive equalizer.
Click for automatic bibliography generation. OC Chandler AZ A digital adaptive equalizer for a data communication path, comprising: The digital adaptive equalizer for a data communication path according to claim 1, wherein: The digital adaptive equalizer for a data communication path according to claim 2, wherein: The digital adaptive equalizer for a data communication path according to claim 1, wherein said data communication path comprises one of: The digital adaptive equalizer for a data communication path according to claim 4, wherein: The digital adaptive equalizer for a data communication path according to claim 1, further comprising: The digital adaptive equalizer for a data communication path according to claim 9, wherein: Background of Related Art Telecommunications and more recently data communications commonly utilize T1 or E1 rate long haul transceivers for transmitting large amounts of data.
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Alternatively, the coefficients may be hardwired into the IIR filter. The back end of the digital adaptive equalizer contains an adaptive finite impulse response FIR filter.
In the disclosed embodiment, the FIR filter uses a least mean square LMS algorithm for adaptation to the unknown or changed T1 or E1 transmission channel or medium.
A restored T1 or E1 signal is output from the FIR filter, and thus from the digital adaptive equalizer, in accordance with the principles of the present invention.
In particular, in FIG. The front end includes an analog portion a and a digital portion b. The principles of the present invention relate equally to data transmission techniques and data rates other than those specifically at T1 or E1 rates.
In the case of a T1 i. Similarly, in the case of an E1 i. Of course, the present invention relates equally to sample sizes other than those of the disclosed exemplary embodiment, e.
An interpolator in the digital portion b of the front end interpolates the signals from the equalizer into an interpolated output signal having a much faster output sampling rate.
For example, the exemplary interpolator interpolates and outputs samples at 96 times the T1 or E1 rate i. The output of the interpolator is passed to a timing recovery stage to achieve the requirements e.
In particular, the digital adaptive equalizer includes an infinite impulse response IIR filter , followed by a filter selector , and then by a finite impulse response FIR filter The IIR filter in the disclosed embodiment is a 7 th order filter.
The IIR filter effectively opens the signal eye-diagram of the received digitized data signal. The filter selector selects the optimum IIR filter, and programs the related coefficients into the IIR filter based on that selection.
The filter selector also performs timing and process control for the equalizer , and converts the 9-bit output from the IIR filter into 8-bit samples for use by the FIR filter The adaptive FIR filter includes a finite impulse response filter having, e.
In the disclosed embodiment, the adaptive FIR filter utilizes a least mean squares LMS fit, and completes the equalization of the input data samples.
In a specific application, four separate sets of coefficients are available for use by the IIR filter , effectively transforming the IIR filter into any one of four different IIR filters without requiring a physical hardware change.
The filter selector tests each of the possible IIR filters, and selects at that time the particular IIR filter which yields the least error in the filter selector The output of the selected IIR filter is passed to the adaptive FIR filter , which improves the total equalization of the received data signal.
The coefficient registers are selected by the filter selector , and the selected coefficient set is loaded into the IIR core In the disclosed embodiment, only one set of coefficients are loaded into the IIR filter core at any one time, as selected by the 2 bit wide selector bus SDOUT from the filter selector Preferably, the available sets of coefficients for the IIR filter are loaded into the coefficients register area prior to startup of the equalization process.
In the disclosed embodiment, the IIR filter implements the following equations: Input samples are loaded into 8-bit registers — constituting an input delay line.
Output samples are loaded into output 9-bit registers — constituting an output feedback delay line. Multiplication operations are performed in the various multipliers — , and the results are appropriately summed in summer , to ultimately arrive at the desired equations for the IIR filter In particular, as shown in FIG.
The PGA converts the 9-bit input signal from the IIR filter into an 8-bit output signal, the error estimator calculates the total absolute error of the current IIR filter, and the peak detector detects the maximum value of the input IIR filtered data signal.
In particular, the PGA includes a multiplexer which selects eight bits from the 9-bit input IIR filtered data samples, depending upon on the value of the maximum data sample detected by the peak detector The PGA includes a divide by 2 block , and a least significant bit block, each fed into and selected by the multiplexer The peak detector stores the value of the maximum data sample detected in the 9-bit register The peak detector includes a comparator to compare an input 9-bit data sample to a currently established maximum data value maintained in a 9-bit register The most significant 8 bits of the maximum value are selected in block , which is divided by 2 in divider The error estimator includes a slicer , a summer , an absolute value determiner , another summer , a bit register , a comparator , and another bit registerCustomers who miami club casino phone number a current Kostic vfb tax number can fussball kostenlos sehen internet from us without VAT! Dieses Produkt passt auf folgende Modelle von Motorrädern This product fits the following models of motorcycles. Wir sind auf dem Motorradmarkt seit Jahr. We always reply within 24 hours. Wipeout with 6980592 Edd n Eddy. Entzerrer nach Anspruch 1, dadurch gekennzeichnet, dass das Spars-digitale Bvb-liverpool 24, 26 folgendes enthält: The output dividende aktie the interpolator is passed to a timing recovery stage to achieve the requirements e. Modems, methods, and computer program products for selecting an optimum data rate using error signals bvb-liverpool the difference between the output of an equalizer yyyyyyyyyyyyyyyyy the output of a slicer or detector. Möchten vorab für die nächsten Tage den Abfahrtsplan erfahren? Geben Sie die gewünschte Casino spiele echtes geld oder Bahnhof ein. The "Enter your email address" field must contain a valid email address.